Designation: Associate Professor

Sergio Bernabé was born in Badajoz, Spain, in 1986. He graduated in Technical Engineering in Computer Systems and Computer Engineering from the University of Extremadura in 2009 and 2010, respectively. In the same year, he obtained the M.Sc. degree in Grid Computer Studies and Parallelism, and in 2012 the M.Sc. degree in Engineering and Architecture Research (specialized in Information and Communications Technologies) from the University of Extremadura. Finally, he received his jointly Ph.D. degree in Computer Science with “Ph.D. International Mention” between the University of Iceland and University of Extremadura in 2014. Nowadays, he is an Assistant Professor of Computer Science at Universidad Complutense, Madrid. He has authored or co-authored more than 40 publications, including 18 Journal Citation Report (JCR) papers.

His main research interests comprise remotely sensed hyper/multi-spectral image analysis, signal processing, and efficient implementations of large-scale scientific problems on high performance computing architectures (low-power multicore processors, graphics processing units (GPUs) and field programmable gate arrays (FPGAs), the Intel Xeon Phi and other custom devices).

Dr. Bernabé has been visiting researchers at several institutions, including the Institute for Applied Microelectronics (IUMA) at the ULPGC (Spain) working under the supervision of Dr. Sebastián López in 2011; the Faculty of Electrical and Computer Engineering, 101 Reykjavik (Iceland) at the University of Iceland working under the supervision of Prof. Jón Atli Benediktsson (Pro Rector of Academic Affairs, 2011-2012 President, IEEE GRSS, Fellow, IEEE and Fellow, SPIE) in 2012; the Computer Vision Laboratory (LVC) at the Catholic University of Rio de Janeiro (Brazil) working under the supervision of Dr. Raul Queiroz Feitosa in 2013.

Dr. Bernabé is a recipient of the GRSS Prize Paper Award ’14 of the IEEE Journal of Selected Topics in Applied Earch Observations and Remote Sensing (JSTARS), for the contribution entitled “A Web-Based System for Classification of Remote Sensing Data” published in JSTARS in August 2013. He is a recipient of the Best Ph.D. Dissertation award at University of Extremadura in 2015.

Dr. Bernabé was IEEE GRSS student member (2012-2013). He currently serves as an active Reviewer of international conferences (IEEE Whispers ’12, ’14, CIARP ’14, EUROCON ’15) and international journals.

 

Luis Piñuel is an Associate Professor of the Department of Computer Architecture and Systems Engineering at the Universidad Complutense de Madrid, Spain. From June 2010 to April 2015 he also served as Academic Secretary of the Physics Faculty at the same University. Previously he was a research assistant at the Acoustic Institute of the Spanish National Research Council (CSIC).  He received his M. Sc. and Ph.D. degrees in Computer Science from the Universidad Complutense de Madrid (UCM) in 1996 and 2003, respectively.

His research interests include computer architecture, high-performance computing,low-power microarchitectures, embedded systems, and resource management for emerging computing systems. In these fields, he is co-author of more than 70 publications in prestigious journals and international conferences, several book chapters and he has advised or co-advised 5 PhD dissertations. Ha has been member of the technical program and organization committee of the some relevant conferences (e.g. HPCA).

Worried about improving knowledge transfer between research institutions and industry, he has directed more than 15 research contracts with different companies (Texas Instruments, Indra, Satlink, …).

Katzalin Olcoz received a Ph.D. degree in Physics in 1997 from the Complutense University (UCM) of Madrid. She has been Associate Professor in the Department of Computer Architecture and System Engineering of the Complutense University since 2000. From 2012 to 2016 she served as head of the department of Computer Architecture and System Engineering of the same university. She was a visiting professor at EPFL (Lausanne, Switzerland) from April to June, 2018.
Within the computer architecture group of the Complutense University, she has been involved in several projects in the field of computer architecture and design automation from high-level specifications, since 1992. Her current research interests focus on high performance computing, energy efficiency and virtualization.

 

Google Scholar Profile: https://scholar.google.es/citations?user=RcHOkwsAAAAJ&hl=es&oi=ao

DBLP: https://dblp.org/pers/hd/o/Olcoz:Katzalin

JUAN CARLOS SAEZ received his Ph.D. in computer science from the Complutense University of Madrid (UCM) in 2011. He is now an Associate Professor in the Department of Computer Architecture at UCM and the Campus Representative of the USENIX international association. Since 2012 he has been teaching different subjects related to Operating Systems and Computer Architecture.

His research interests include operating systems, scheduling, runtime systems, multicore architectures, and resource management. His recent research activities focus on improving the interaction between the system software and the architecture for emerging hardware platforms.

Publications

2024

J. Rubio, C. Bilbao, J. C. Saez and M. Prieto-Matias. Exploiting Elasticity via OS-runtime Cooperation to Improve CPU Utilization in Multicore Systems. 32nd Euromicro International Conference on Parallel, Distributed, and Network-Based Processing – PDP ’24 (2024). PDF

2023

C. Bilbao, J. C. Saez and M. Prieto-Matias. Divide&Content: A Fair OS-Level Resource Manager for Contention Balancing on NUMA Multicores. IEEE Transactions on Parallel and Distributed Systems, vol. 34, no. 11, pp. 2928-2945, Nov. 2023, DOI: 10.1109/TPDS.2023.3309999. Download open-access article in PDF here

C. Bilbao, J. C. Saez and M. Prieto-Matias. Revisiting Fairness and Throughput Metrics for Cache-Partitioning Policy Assessment: Insights and Recommendations. 1st Workshop on Computer Architecture Modeling and Simulation (CAMS ’23) In conjunction with MICRO ’23 (2023).

C. Bilbao, J. C. Saez and M. Prieto-Matias. Flexible system software scheduling for asymmetric multicore systems with PMCSched: A case for Intel Alder Lake. Concurrency and Computation: Practice and Experience. 2023; 35(25):e7814. DOI: 10.1002/cpe.7814. PDF

2022

C. Bilbao, J. C. Saez and M. Prieto-Matias. Rapid development of OS support with PMCSched for scheduling on asymmetric multicore systems. Proceedings of Euro-Par 2022: Parallel Processing Workshops (2022). Springer. DOI: 10.1007/978-3-031-31209-0_14. PDF

J. C. Saez, F. Castro, G. Fanizzi and M. Prieto-Matias, LFOC+: A Fair OS-Level Cache-Clustering Policy for Commodity Multicore Systems. IEEE Transactions on Computers, vol. 71, no. 8, (2022): pp. 1952-1967. ISSN: 0018-9340. DOI: 10.1109/TC.2021.3112970. PDF

2020

J.C. Saez, F. Castro, M. Prieto-Matias: Enabling performance portability of data-parallel OpenMP applications on asymmetric multicore processors. Proceedings of the 49th International Conference on Parallel Processing (ICPP ’20): pp. 51:1–51:11. (2020) ACM.ISBN: 978-1-4503-8816-0. DOI: 10.1145/3404397.3404441.

A. Garcia-Garcia, J.C. Saez, J.L. Risco-Martin, M. Prieto-Matias: PBBCache: an open-source parallel simulator for rapid prototyping and evaluation of cache-partitioning and cache-clustering policies. Journal of Computational Science, 42: article 101102 (2020).  ISSN: 1877-7503.

2019

A. Garcia-Garcia, J.C. Saez, F. Castro, M. Prieto-Matias: LFOC: A Lightweight Fairness-Oriented Cache Clustering Policy for Commodity Multicores. Proceedings of the 48th International Conference on Parallel Processing (ICPP ’19): pp. 14:1–14:10. (2019) ACM.ISBN: 978-1-4503-6295-5. DOI: 10.1145/3337821.3337925.

A. Garcia-Garcia, J.C. Saez, F. Castro, M. Prieto-Matias: Particionado eficiente de cache en cluster para mejorar la justicia en procesadores multicore comerciales. Jornadas SARTECO 2019: pp. 162–171. (2019). ISBN: 978-84-09-12127-4.

2018

A. Garcia-Garcia, J.C. Saez, M. Prieto-Matias: Contention-aware fair scheduling for asymmetric Single-ISA multicore systems. IEEE Transactions on Computers, 67 (12): pp. 1703-1719. (2018). ISSN: 0018-9340. DOI: 10.1109/TC.2018.2836418

R. Rodríguez-Rodríguez, J. Díaz, F. Castro, P. Ibañez, D. Chaver, V. Viñals, J.C. Saez, M. Prieto-Matias, L. Piñuel, T. Monreal, J.M. Llabería: Reuse Detector: Improving the Management of STT-RAM SLLCs. Computer Journal, 61 (6): pp. 856-880. (2018). ISSN: 0010-4620. DOI: 10.1093/comjnl/bxx099

J.C. Saez, A. Pousa, A.E. De Giusti, M. Prieto-Matias: On the Interplay between Throughput, Fairness and Energy Efficiency on Asymmetric Multicore Processors. Computer Journal, 61 (1): pp. 74-94. (2018). ISSN: 0010-4620. DOI: 10.1093/comjnl/bxx038

2017

A. Garcia-Garcia, J.C. Saez, M. Prieto-Matias: Optimización de la justicia en procesadores multicore asimétricos mediante planificación consciente de la contención. Jornadas SARTECO 2017: pp. 255–264. (2017). ISBN: 978-84-697-4835-0.

A. Garcia-Garcia, J.C. Saez, M. Prieto-Matias: Delivering fairness on asymmetric multicore systems via contention-aware scheduling. Euro-Par 2017: Parallel Processing Workshops, Lecture Notes on Computer Science. 5th Workshop on Runtime and Operating Systems for the Many-core Era , LNCS 10659: pp. 610–622. (2017) Springer.ISBN: 978-3-319-75177-1. DOI: 10.1007/978-3-319-75178-8_49.

J.C. Saez, A. Pousa, F. Castro, D. Chaver, M. Prieto-Matias: Towards completely fair scheduling on asymmetric single-ISA multicore processors. Journal of Parallel and Distributed Computing, 102: pp. 115-131. (2017). ISSN: 0743-7315 . DOI: 10.1016/j.jpdc.2016.12.011

J.C. Saez, A. Pousa, R. Rodriguez-Rodriguez, F. Castro, M. Prieto-Matias: PMCTrack: Delivering performance monitoring counter support to the OS scheduler. Computer Journal, 60 (1): pp. 60-85. (2017). ISSN: 0010-4620. DOI: 10.1093/comjnl/bxw065

2015

J.C. Saez, J. Casas, A. Serrano, R. Rodriguez-Rodriguez, D. Chaver, M. Prieto: An OS-Oriented Performance Monitoring Tool for Multicore Systems. Euro-Par 2015: Parallel Processing Workshops, Lecture Notes on Computer Science. 3rd Workshop on Runtime and Operating Systems for the Many-core Era , LNCS 9523: pp. 697–709. (2015) Springer.ISBN: 978-3-319-27307-5. DOI: 10.1007/978-3-319-27308-2_56.

J.C. Saez, A. Pousa, D. Chaver, M. Prieto: ACFS: A Completely Fair Scheduler for Asymmetric Single-ISA Multicore Systems. Proceedings of the 30th ACM/SIGAPP Symposium On Applied Computing (SAC 2015): pp. 2027–2032. (2015) ACM.ISBN: 978-1-4503-3196-8. DOI: 10.1145/2695664.2695714.

2014

A. Pousa, J.C. Saez, A.E. De Giusti, M. Prieto: Evaluación de algoritmos de planificación sobre un prototipo de sistema multicore asimétrico. XX Congreso Argentino de Ciencias de la Computación (CACIC’14): pp. 264–173. (2014). ISBN: 978-987- 3806-05-6.

J.C. Saez, A. Pousa, F. Castro, D. Chaver, M. Prieto: Exploring the Throughput-Fairness Trade-off on Asymmetric Multicore Systems. Euro-Par 2014: Parallel Processing Workshops, Lecture Notes on Computer Science. 2nd Workshop on Runtime and Operating Systems for the Many-core Era , LNCS 8806: pp. 326–337. (2014) Springer.ISBN: 978-3-319-14312-5. DOI: 10.1007/978-3-319-14313-2_28.

2013

J.C. Saez, A. Pousa, D. Chaver, M. Prieto: Explotando el Compromiso Rendimiento-Justicia en Procesadores Multicore Asimétricos mediante Planificación. XXIV Jornadas de Paralelismo: pp. 49–54. (2013). ISBN: 978-84-695-8330-2.

S. Zhuravlev, J.C. Saez, S. Blagodurov, A. Fedorova, M. Prieto: Survey of energy-cognizant scheduling techniques. IEEE Transactions on Parallel and Distributed Systems, 24 (7): pp. 1447-1464. (2013). ISSN: 1045-9219. DOI: 10.1109/TPDS.2012.20

J.C. Saez, F. Castro, D. Chaver, M. Prieto: Delivering Fairness and Priority Enforcement on Asymmetric Multicore Systems via OS Scheduling. Proceedings of the ACM SIGMETRICS/International Conference on Measurement and Modeling of Computer Systems (SIGMETRICS’13): pp. 343–344. (2013) ACM.ISBN: 978-1-4503-1900-3. DOI: 10.1145/2494232.2465532.

2012

S. Zhuravlev, J.C. Saez, S. Blagodurov, A. Fedorova, M. Prieto: Survey of Scheduling Techniques for Addressing Shared Resources in Multicore Processors. ACM Computing Surveys, 45(1). Art. 4: pp. 1-28. (2012). ISSN: 0360-0300 . DOI: 10.1145/2379776.2379780

J.C. Saez, A. Fedorova, D. Koufaty, M. Prieto: Leveraging core specialization via os scheduling to improve performance on asymmetric multicore systems. ACM Transactions on Computer Systems, 30(2). Art. 6: pp. 1-38. (2012). ISSN: 0734-2071 . DOI: 10.1145/2166879.2166880

2011

J.C. Saez, A. Pousa, A. Fedorova, M. Prieto: Explotación de Técnicas de Especialización de Cores para Planificación Eficiente en Procesadores Multicore Asimétricos. XXII Jornadas de Paralelismo: pp. 245–250. (2011). ISBN: 978-84-694-1791-1.

J.C. Saez, D. Shelepov, A. Fedorova, M. Prieto: Leveraging workload diversity through OS scheduling to maximize performance on single-ISA heterogeneous multicore systems. Journal of Parallel and Distributed Computing, 71(1): pp. 114-131. (2011). ISSN: 0743-7315 . DOI: 10.1016/J.JPDC.2010.08.020

2010

J.C. Saez, A. Fedorova, M. Prieto, H. Vegas: Operating System Support for Mitigating Software Scalability Bottlenecks on Asymmetric Multicore Processors. Proceedings of the 7th ACM international Conference on Computing Frontiers (CF ’10): pp. 31–40. (2010) ACM.ISBN: 978-1-4503-0044-5. DOI: 10.1145/1787275.1787281.

J.C. Saez, M. Prieto, A. Fedorova, S. Blagordurov: A Comprehensive Scheduler for Asymmetric Multicore Systems. Proceedings of the 5th ACM European Conference on Computer Systems (EuroSys’10): pp. 139–152. (2010) ACM.ISBN: 978-1-60558-577-2. DOI: 10.1145/1755913.1755929.

2009

A. Fedorova, J.C. Saez, D. Shelepov, M. Prieto: Maximizing power efficiency with asymmetric multicore systems. Communications of the ACM, 52(12): pp. 48-57. (2009). ISSN: 0001-0782 . DOI: 10.1145/1610252.1610270

A. Fedorova, J.C. Saez, D. Shelepov, M. Prieto: Maximizing Power Efficiency with Asymmetric Multicore Systems: Asymmetric multicore systems promise to use a lot less energy than conventional symmetric processors. How can we develop software that makes the most out of this potential?. ACM Queue, 7 (10): pp. 30-45. (2009). ISSN: 1542-7730 . DOI: 10.1145/1647300.1658422

J.C. Saez, H. Vegas, A. Fedorova, M. Prieto: Planificación en Multicore Asimétricos con Repertorio Común de Instrucciones. XX Jornadas de Paralelismo: pp. 379–386. (2009). ISBN: 84-9749-346-8.

J.C. Saez, A. Fedorova, M. Prieto, H. Vegas: Scheduling for ASISA multicore processors. Advanced Computer Architecture and Compilation for Embedded Systems (ACACES ’09): pp. 179–182. (2009). ISBN: 978-90-382-1467-2.

D. Shelepov, J.C. Saez, S. Jeffery, A. Fedorova, N. Perez, Z. Huang, S. Blagodurov, V. Kumar: HASS: A scheduler for heterogeneous multicore systems. Operating Systems Review, 43 (2): pp. 66-75. (2009). ISSN: 0163-5980. DOI: 10.1145/1531793.1531804

2008

J.C. Saez, J.I. Gomez, M. Prieto: Improving priority enforcement via non-work-conserving scheduling. Proceedings of the 37th International Conference on Parallel Processing (ICPP ’08): pp. 99–106. (2008) IEEE Computer Society.ISBN: 978-0-7695-3374-2. DOI: 10.1109/ICPP.2008.38.

José Ignacio Gómez Pérez received the M.Sc. degree in Computer Science in 2001 and the Ph.D. degree in 2007, all from the Complutense University of Madrid, Spain. He is currently Associate Professor with the Department of Computer Architecture and Automation, UCM, within the ArTeCS group.

During his Ph.D., José Ignacio was a visiting research at Imec (Leuven),  working on optimizing low-power embedded systems, both at the compiler and system level. After his Ph.D. he moved to GPGPU computing, still at the compiler level.

At present,  his current research interests include low power embedded systems, focusing on architectural impact of new resistive memory technologies,  in the IoT ecosystem.

Joaquin Recas Piorno received the M.Sc. degree in Computer Science from the Autónoma University of Madrid, Spain, in 2000. He also received the M.Sc. degree in Electronics and the Ph.D. degree in Computer Science from the Complutense University of Madrid (UCM), Spain, in 2004 and 2006, respectively. He is currently Assistant Professor with the Department of Computer Architecture and Automation, UCM, within the ArTeCS group.

His current research interests include low power embedded systems applied to real-time signal processing.

 

Francisco D. Igual obtained the MS degree in Computer Engineering from University Jaume I de Castellón (Spain) in 2006, and the Ph.D. degree in Computer Science from the same University in 2011. In 2011, he joined the University of Texas at Austin as a postdoctoral researcher, and in 2012, he joined the Department of Computer Architecture from the University Complutense of Madrid as a Juan de la Cierva Fellow. Since 2020, he is an associate professor at the same University.

His research interests include high-performance and energy-aware computing, dense linear algebra library development and optimization (collaborating with the SHPC group at the University of Texas at Austin), and runtime task scheduling on massively heterogeneous architectures. He has co-authored more than 50 papers on journals and conferences in the aforementioned fields.

[mendeley type=groups id=fe45c347-c705-338d-beb4-85c2b70285bf groupby=year filter=author=Igual style=cover]

Fernando Castro obtained the MS degree in physics from University of Santiago de Compostela in 2000, the MS degree in electrical engineering and the Ph.D. degree in computer science from the University Complutense of Madrid (UCM) in 2004 and 2008, respectively. He is now an associate professor in the Department of Computer Architecture, UCM. His research interests include energy-aware processor design, efficient memory management and OS scheduling on asymmetric multiprocessors. His recent activities also focused on the software engineering, exploring new tools aiming to improve the classroom teaching.

Daniel A. Chaver Martínez studied Physics at the University of Santiago de Compostela (USC) from 1994 to 1998 and Electrical Engineering at University Complutense of Madrid (UCM) from 1998 to 2000. He developed his PhD from 2000 to 2006 at UCM. He has tought many different courses related to Computer Science and Electrical Engineering since 2000. He was the Academic Secretary of the Department of Computer Architecture since 2006 until 2015. His current research interests include: Architectural Techniques for the Cache and for Non-volatile Memories and OS Scheduling for Asymmetric MultiProcessors. Since mid-2015, he is collaborating with Imagination-MIPS in some of their products.

Christian Tenllado received the M.Sc. degree in Electronics Engineering in 2001 and the Ph.D. degree in Computer Architecture in 2007, all from the Complutense University of Madrid, Spain. He also received the M.Sc. degree in Physics from the Open University of Spain (UNED) in 2003. He is currently Associate Professor with the Department of Computer Architecture and Automation, UCM, within the ArTeCS group.

During his Ph.D., Christian Tenllado worked on the efficient exploitation of SIMD instruction sets. During that period he was a visiting researcher at Imec (Leuven),  working within the group of Francky Catthoor. After his Ph.D. he moved to GPGPU computing, tackling both manual application mapping and compiler level mapping techniques.

At present,  his research moved to low power embedded systems and accelerators. We are currently considering the impact of new resistive memory technologies in the IoT ecosystem.