I am currently a research fellow at IMEC, Heverlee, Belgium. I received the Eng. degree and a Ph.D. in El. Eng. from the K.U.Leuven, Belgium in 1982 and 1987 respectivel. In both cases, I obtained summa cum lauda and, in the case of his PhD, with felicitations of the jury. In 1986 I received the Young Scientist Award from Marconi International Fellowship Council. Since 1983, I have been lecturer for different courses ath the Electrical Engineering Department of K.U. Leuven. I I have been co-advisor of more tan 100 PhD students, many of them at universities outside Leuven. I am also co-responsible for supervision and assessment of master’s theses.
Since 1987, I have headed research domains in the area of architectural and system-level synthesis methodologies, within the DESICS (formerly VSDM) division at IMEC. At 2011 I became chief sicentist in the Design Technology for Integrated Information and Communication Systems Division and, from 2003 I am a research fellow of Imec, nvolved especially in inter-divisional activities and co- operation, partly including also co-operation with university groups in the so-called Sandwich PhD network .
Up to now about 800 papers have been authored or co-authored in international (reviewed) conferences, journals and books. Three of the papers obtained the Best paper award in their respective conferences. I have given more tan 10 invited talks in internation conferences and participated in may panel contribtuions. Only in 1996 my division at IMEC tarted submitting patents on their research results, Since then, he has been co-author of more than 60 submitted patents.
I have been member of program committee or review commitee in many conferences and workshops including Application-specific array processing (ASAP) , Electronic Design and Test (EDAC/EDTC), Intnl. Conf. on Computer-Aided Design (ICCAD), High-level/System-level synthesis workshop, Intnl. System-level synthesis symposium (ISSS), VLSI Signal Processing Workshop, IEEE Workshop on Signal Processing Systems (SiPS), EuroPar Conference,
High-level Design Validation and Test Conf,
Intnl. Symp. on Low Power Design (ISLPED), IEEE Micro and ISCAS. I have been Associate editor for the IEEE Trans. on VLSI Systems, IEEE. Trans on Multi-Media, ACM Trans. on Design Automation ofr Embedded Systems and the Kluwer Journal of VLIST Singal Processing. I have been Member of ”Steering Board of the VLSI Technical Committee of the IEEE Circuits & Systems Society”, since 1997, representative for the ”IEEE Trans. on VLSI Systems” (VSATC) Steering Committee, since 1999; Member of ”Digital Signal Proc. Systems (DISPS) Technical Committee of the IEEE Signal Proc. Society”, since 2002; member of 2009 and 2011 Circuits and Systems Society (CAS) IEEE Fellow Selection Committees.
My current research activities belong to the field of architecture design methods and system-level exploration for power and memory footprint within real-time constraints, oriented towards data storage management, global data transfer optimization and concurrency exploitation. Platforms that contain both customizable/configurable architectures and (parallel) programmable instruction-set processors are targeted.