There is an open PhD position at Artecs group. The PhD work will be jointly supervised by Imec, vzw so the student will obtain a dual PhD degree: Universidad Complutense de Madrid and KULeuven.
The description of the PhD goal is given below. For more information please contact firstname.lastname@example.org
Stack data placement in hybrid scratchpad-cache hierarchies
The Internet of Things (IoT) paradigm has become a reality as many objects that surround us are connected to the Internet, providing a huge variety of new services. Many technologies involved in this revolution: wireless communication, ultra-low power processes, embedded sensors radio frequency identification… and all of them are constantly evolving to meet ever increasing application requirements.
At device level, low energy consumption is a must, since devices need to be battery operated. Regarding simple sensor nodes, like temperature or humidity sensors used in smart home applications, CPU activity is very low and most of the energy is spent sending the data through the available wireless interface. However, applications of domains like healthcare do require relevant processing before transmitting data so CPU energy consumption gets significantly increased.
Focusing on the latter application domains, the memory system arises as the main source of energy consumption. Traditional hardware controlled caches, designed to reduce overall memory access latency, add a significant energy overhead due to their complex controllers and the inherent speculation when transferring data. Moreover current on-chip memory technologies, specially SRAM, is endangered due to transistor scaling. New magnetic technologies, like STT-RAM and SoT-RAM, are arising and appear as potentially promising candidates to replace SRAM at every layer of cache hierarchy.
This PhD aims to explore software controlled memories (scratchpad) as a lower energy alternative to hardware controlled caches. Both, fully magnetic and hybrid SRAM- magnetic hierarchies are to be considered. In order to narrow the scope of the exploration, the PhD main goal will be to design mapping strategies for stack data onto a multi-scratchpad memory organization. In many applications, the vast majority of memory accesses target the run-time stack. Its dynamic nature prevents fully mapping it onto small energy-efficient scratchpad memory. Thus, a methodology needs to be developed to decide which parts of the stack benefit more from scratchpad mapping.
Finally, a mechanism to enforce this mapping has to be envisaged. However, a couple of restrictions apply to this end. Most of the time, application source codes are not be available to recompile, so traditional compiler techniques will not be applicable. Binary instrumentation will be the preferred way to profile the application and (if required) modify the code.
Furthermore, industry would be reluctant to modify the CPU data path; thus, new hardware proposals should be restricted to the memory subsystem and remain transparent to existing unmodified binaries.