In the near future, portable consumer devices must run multimedia and wireless network applications that require an enormous computational performance at a low energy consumption. These multimedia and wireless network applications generally are interactive and dynamic in nature.Current embedded systems are determined at a very high-level (e.g. C++ or Java) trying to achieve mainly modularity while platform-dependent optimizations are done only at design time much later, in the final mapping phase. Thus, the programmers select fixed implementations that are designed for maximum worst-case load. Such an implementation will usually be over-dimensioned in most of the cases and will hence waste cost and power, so the most common solution is to select a cheaper implementation that will occasionally suffer performance problems.
One of the goals of this research line is to develop the necessary new methodologies to overcome the aforementioned present design limitations and to suitably implement this highly dynamic new multimedia applications (e.g. MPEG-4 video systems, Quality of Service (QoS) 3D rendering, 3D games, etc.) in current embedded and portable consumer devices. Therefore, we refine the systems and applications at their different abstraction levels thus starting from the needed very high-level specification, i.e. C++ or Java, to the final hardware/software implementation on embedded devices. Key steps of this process include: optimization of the dynamic data types used by the algorithm to interact with the dynamic memory subsystem, optimization of dynamic memory de/allocations; task concurrency management, and physical memory management.
Network-on-Chip (NoC) has emerged as a promising paradigm for designing scalable communication architecture for Systems on Chip (SoC). In NoCs, instead of the traditional non-scalable buses, on-chip micro-networks are used to interconnect the various cores. NoCs have initially better modularity and design predictability when compared to bus based systems; However, in order to become really usable in real-life systems, an application-specific NoC with structured wiring, which satisfies the design objectives and constraints, is mandatory to have working NoCs at high frequency.
Another goal of this research line is the development of a methodology to design the best topology that is tailor-made for a specific application and satisfies the communication constraints of the design. The developed topology design process must support constraints on several parameters such as the hop-delay (when the objective is power minimization), network power consumption (when the objective is hop-delay minimization), design area and total wire-length. In the presented topology design the synthesis process uses a floorplanner to estimate the design area and wire-lengths. The wire-length estimates from the floorplan are used to evaluate whether the designed NoC satisfies the target frequency of operation and to compute the power consumption of the wires.