Welcome to our GitHub repositories, where the ArTeCS group shares cutting-edge open‑source projects in computer architecture, parallel computing, and emerging numeric systems. Explore our work—from RISC‑V cores and FPGA‑based simulations to posit‑arithmetic accelerators, compiler toolchains, and portable benchmarks—covering both teaching tools and research-grade implementations aimed at advancing hardware/software co-design and performance portability.
Here are some standout projects that exemplify our group’s contributions:
- PERCIVAL – An open-source Posit RISC‑V core enhanced with quire support, implemented in C++, showcasing our research in alternative number systems.
- RVfpga‑sim‑addons – A suite of simulation tools tailored for RVfpga FPGA teaching environments, developed in collaboration with Imagination Technologies.
- posit‑hls – High‑Level Synthesis implementations of posit‑arithmetic accelerators, supporting reproduction of experiments from our IEEE T-CAS I paper.
- Juliana.jl – A Julia‑based code translation tool that converts CUDA.jl kernels into multi‑backend formats via KernelAbstractions.jl; introduced in PPAM 2024.