TIN 2012-32180 ARTE Arquitecturas y tecnologías emergentes. Eficiencia energética mediante

1/1/2013 – 31/12/2015


The research in this project is focused on the high performance computing area and address several of the challenges that currently limit the performance scaling of computing systems. Overall, these scaling problems are caused by failures on the two main pillars that where used in the past to improve performance (Dennard’s scaling theory and aggressive mechanism for exploiting instruction level parallelism). Limitations are so severe that require a holistic view, being necessary deep changes at most levels (technology, microarchitecture, system software and applications), and opening up new and interesting research opportunities. Within this wide landscape, we have structured this project into three broad areas that build on the previous research experience of the group:

  1. Efficient management of multicore architectures. There is still some room to enhance the performance of multicore architecture since in many cases, computer architects have reused some components and policies that were originally designed for single-core architectures. At the micro-architectureal level, the project will seek to improve the management of shared cache levels. At the system level, we will explore energy-aware scheduling algorithms in the context of asymmetric multicore platforms.
  2. Architectural level solutions for emerging memory technologies. Non-volatile resistive memories will play a crucial role when designing alternative memory hierarchies. However, even if the potential of such memories is huge (both from the energy and area point of view), they exhibit severe limitations in critical aspects (durability and write latency). We will explore hybrid memory hierarchies trying to keep the best of both worlds.
  3. Exploitation of Hardware accelerators. Current homogeneous multicore architectures scalability is threatened by power consumption and dissipation. Dark silicon and other phenomena will cause a shift towards more hardware specialization. Managing this additional heterogeneity will require new techniques to efficiently develop software. Both, compile techniques and application implementations, are highly required to evolve in the near future. Both topics have been addressed in this project. We will consider the polyhedral-model to assist the design/compilation process when applications are to be mapped onto many-core architectures with complex memory hierarchies. At application level, we will devise new implementation techniques to efficiently exploit hardware accelerators in the context of signal processing, cryptography and similarity search applications.