Hardware/software architecture for high-performance systems II
Funding entity : National Science Agency (TIN2008-00508)
Principal Investigator : Francisco Tirado Fernández
Participating entities : Complutense University of Madrid
Starting date : 01.01.2009 Ending date : 06.30.2015
Project amount : 1,217,260 €
This project proposes a set of interacting research lines that face the conception of new high-performance computing systems, as well as, its efficient exploitation in terms of processing speed, energy consumption and cost. Within this frame, the project covers two main working areas:
- High Performance Computing. Future improvements in processor performance will predominantly come from Thread/Memory Level Parallelism, rather than from an increasing clock frequency or processor complexity. In this project we will address some of the issues that arise within this challenging scenario. At the architecture level, our goal is to improve the memory model and some specific aspects of the HW/SW interface. Other topics covered by this area at the system and application levels are: code generation and optimization, runtime resource management and application mapping for large scale chip multiprocessors.
- Embedded systems. System-on chip (SoC) architectures have become a very attractive solution to address complexity and time-to-market pressure in the new consumer multimedia embedded market. However, although the SoC paradigm tries to simplify the complexity issues of latest high-performance embedded systems, their suitable design and development involve important challenges in various conflicting design metrics (power, performance, reliability), in the areas of on-chip interconnect, data-processing hardware design (made of processors and specific circuits), and interaction of multiple software levels (application design, dynamic memory management, operating system), that will be addressed in this project.