System level management of hybrid memory systems



This project, carried out in cooperation with IMEC, aim to explore the architectural impact of different resistive memory technologies. On the one hand, we are building new models for STT-RAM,  the most promising of the plethora of NVM technologies that appeared in the past recent years. Current models are not accurate enough regarding latency and energy per access since STT-RAM technology is evolving fast and past assumptions have are no longer valid today. On the other hand, a complete architectural exploration will be performed to evaluate the impact of NVM technologies at different levels of the memory hiearchy.