Nowadays, HEVC is the most interesting and cutting-edge topic in the world of digital video compression. From TVs to cell phones and camcorders to PCs, most consumer electronic devices utilize video applications, which rely on video compression. The improvements performed over the video encoding products have thus a tremendous social impact. Ranging from professional communication equipments to conventional cell phone users, all of them may benefit from the techniques developed in this project. We research on algorithmic solutions as well as low-power implementations which will also impact economically.
Next-generation HEVC/H265 compression provides 50% bit rate reduction compared to H.264, resulting in the delivery of high quality video at lower bit rates. Thus, the required network bandwidth is also reduced almost by half in comparison with the H.264 standard. As a consequence of this, HEVC diminishes the costs associated with dedicated satellite, cellular and broadband network pipes. This also brings the possibility of streaming 4K videos over 4G in the near future. Besides the bandwidth reduction, the era of the heterogeneous computing opens new possibilities to tackle performance problems through low-power and low-cost platforms.
We actually works on the integration of HEVC since the release of the new standard, being the main goal of the project is to provide the best-in class video encoding quality for a HEVC-based encoder, utilizing a low-power and low-cost heterogeneous platform. Video compression standards define the format of a compressed video sequence, as well as a method to decode a compressed sequence. However, the design of the encoder is not standardised. Decoders do not provide neither quality nor compression efficiency, as their main function is to obtain an image from a standard bitstream. For this reason, it is important to understand that not all HEVC encoders are equally implemented. The compression efficiency as well as the video quality directly depend on the encoder design.
This research line will meet the rigorous demands required for the tremendous HD/UHD/HEVC processing power, while providing superior video quality and motion fluency. Summarizing, all in all allowing the customers a higher video quality, at a lower power and monetary budget.
Motion estimation from image sequences, called optical flow, has been deeply analysed by the scientific community. Despite the number of different models and algorithms, none of them covers all problems associated with real-world processing. This research line focuses on design ad-hoc architectures (FPGAs) as well as accelerate high computationally intensive robust optical flow algorithms (GPGPUs, Multicores, DSPs) useful in many tasks such as surveillance, tracking, navigation, atmospheric sciences, robotic, automotive, etc…
Numerous ways of communication in our networked society enables easy and instant sharing of digital images. In scope of computational photography, this presents an opportunity for a promotion and a way to do business. However, it also presents a problem since it is very easy for someone to reshare the images and violate copyrights of the original owner. To mitigate this problem there are various methods for the protection of the ownership of digital images such as data hiding or image watermarking.
We works on steganographic methods for real time data hiding. The main goal of the research is to develop high capacity steganographic methods with increased robustness to unintentional image processing attacks. In addition, we prove the validity of the method in real time applications. The approaches are based on a different mathematical transforms where the values of coefficients are modified in order to hide data. This modification is invisible to the human observer. We further the investigation by implementing proposed method in different target architectures and analyse their performance. Results currently show that the proposed method are robust to image compression, scaling and blurring. In addition, modification of the image is imperceptible even though the number of embedded bits is high. We currently works on the implementation of the proposed method on four different portable and low-cost target architectures.